Simple method for making smaller microchip patterns

For the last few decades, microchip manufacturers have been on a quest to find ways to make the patterns of wires and components in their microchips ever smaller, in order to fit more of them onto a single chip and thus continue the relentless progress toward faster and more powerful computers. That progress has become more difficult recently, as manufacturing processes bump up against fundamental limits involving, for example, the wavelengths of the light used to create the patterns.

Now, a team of researchers at MIT and in Chicago has found an approach that could break through some of those limits and make it possible to produce some of the narrowest wires yet, using a process with the potential to be economically viable for mass manufacturing with standard types of equipment.

The new findings are reported this week in the journal Nature Nanotechnology, in a paper by postdoc Do Han Kim, graduate student Priya Moni, and Professor Karen Gleason, all at MIT, and by postdoc Hyo Seon Suh, Professor Paul Nealey, and three others at the University of Chicago and Argonne National Laboratory. While there are other methods that can achieve such fine lines, the team says, none of them are cost-effective for large-scale manufacturing.

The new approach includes a technique in which polymer thin films are formed on a surface, first by heating precursurs so they vaporize, and then by allowing them to condense and polymerize on a cooler surface, much as water condenses on the outside of a cold drinking glass on a hot day.

“People always want smaller and smaller patterns, but achieving that has been getting more and more expensive,” says Gleason, who is MIT’s associate provost as well as the Alexander and I. Michael Kasser (1960) Professor of Chemical Engineering. Today’s methods for producing features smaller than about 22 nanometers (billionths of a meter) across generally require either extreme ultraviolet light with very expensive optics or building up an image line by line, by scanning a beam of electrons or ions across the chip surface — a very slow process and therefore expensive to implement at large scale.

The new process uses a novel integration of three existing methods. First, a pattern of lines is produced on the chip surface using well-established lithographic techniques, in which an electron beam is used to “write” the pattern on the chip.